FIG. 3 shows a circuit diagram of an input portion of ASOO NAND Gate Schematic shown in page 7 of Advanced Schottky Family Application Report of Texas Instruments Corporation. In FIG. 3, the reference numeral 1 designates an input terminal, the reference numeral 2 designates a PNP transistor, the reference numeral 3 designates an input schottky barrier diode (hereinafter referred to as "SBD"), the reference numeral 4 designates an input clamping SBD, and the reference numeral 5 designates an NPN transistor for increasing the surge resistivity.
FIG. 4 is a circuit diagram showing the portion relating to the surge resistivity extracted from the circuit of FIG. 3, and FIG. 5 is a cross-sectional view showing the IC structure for realizing the circuit of FIG. 4. In the FIGS. 4 and 5, the reference numeral 6 designates an N type epitaxial layer, and this is used as the collector of the NPN transistor 5. The reference numerals 7 and 8 designate P.sup.+ and N.sup.+ layer produced on the surface of the epitaxial layer 6, respectively, and they are used as the base and the emitter of the NPN transistor 5. The reference numeral 9 designates an aluminum wiring connected to the internal circuit of the IC. The reference numeral 10 designates an aluminum wiring of the ground level. The reference numeral 11 designates an N.sup.+ layer provided so as to reduce the resistance component between the input terminal 1 and the collector 6. The reference numeral 12 designates an N.sup.+ layer provided so as to reduce the resistance component between the N.sup.+ layer 11 and the collector 6. The reference numeral 13 designates an N.sup.+ embedded layer of the ground level provided so as to prevent the operation of the parasitic element. The reference numeral 14 designates a P.sup.+ layer of the ground level provided to prevent the current leakage between the N.sup.+ embedded layers 12 and 13. The reference numeral 15 designates a P type substrate, and the reference numeral 16 designates an oxide film provided to separate the epitaxial layer 6 and the other epitaxial layer (not shown). The reference numeral 17 designates an oxide film provided to protect the surface of the epitaxial layer 6. FIG. 6 shows the at breakdown voltage vs current characteristics (base-emitter short characteristics) of the NPN transistor 5.
The operation of the device when the surge voltage is applied will be described.
When a surge voltage is applied to the input terminal 1, if there is not provided an NPN transistor 5, an overcurrent flows through the input SBD 3, and a large power is consumed at the input SBD 3 because the breakdown voltage of the input SBD 3 is relatively high, that is, about 30 V, and the input SBD 3 is easily destroyed. Actually, there is an NPN transistor which shows the characteristics of FIG. 6, and when a surge voltage is applied the NPN transistor 5 enters the breakdown state, and an overcurrent does not flow through the input SBD 3. Then, the transistor 5 shows a low breakdown maintaining voltage of about 7 V, and this voltage is sufficiently low with relative to the breakdown voltage of the input SBD 3, and a large portion of the surge current flows through the NPN transistor 5.
By the way, in the transistor 5 the voltage drop at the junction portion is small and the power concentration on the junction portion is small, and the area of the junction portion is enlarged to a value larger than that of the input SBD 3, thereby reducing the power consumption per a unit area. Accordingly, even if a large current flows through the NPN transistor 5, the NPN transistor 5 is not likely to be destroyed with relative to the input SBD 3, and thus it is possible to enhance the anti input surge distraction resistivity to a great extent by using the NPN transistor 5.
The input portion of the prior art semiconductor integrated circuit device is constructed in such a manner, and the input portion has a breakdown maintaining voltage of about 7 V, but in a device having this characteristics there is a possibility that this characteristics does not satisfy the regulation that the input voltage resistivity is 7 V depending on the way of use. That is to say, it is expected that a variation of about 1 V exists in the breakdown maintaining voltage, and when it is supposed that the prior art devices are produced, there may be produced a lot of devices having an input portion which has a breakdown maintaining voltage less than 7 V. Furthermore, when an input voltage larger than 35 V is applied temporarily in such a prior art device, a large current flows continuously even if the input voltage is reduced to 7 V. Although it cannot be necessarily said that such a device is out of regulation, it is quite undesirable.